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HP28S PROCESSOR NOTES Version 1
Copyright (C) 1989, Alonzo Gariepy
================================================================
The next several postings contain my notes on the HP28's CPU. The
information they hold should be sufficient for you to start machine
language programming your calculator. I make no claims about their
quality or fitness for any particular purpose. Please inform me of
any errors. I'm on the net at <uunet!microsoft!alonzo>.
Copyright (C) 1989 Alonzo M. Gariepy.
These notes are divided into four sections:
HP28S PROCESSOR NOTES
HP28S PROCESSOR ARCHITECTURE
HP28S PROCESSOR INSTRUCTION SET
HP28S MACHINE CODE USERS GUIDE
Future notes may include:
HP28S ASSEMBLER/DISASSEMBLER IN PROLOG
HP28S MEMORY MANAGEMENT
HP28S HARDWARE
HP28S BIBLIOGRAPHY
These notes may not be distributed for profit without the written
consent of the author.
______________________________________________________________________
I have completely reorganized and renamed the instruction set for my
own purposes. This may render these notes of no value to some people,
for which I am sorry. The new oganization and names have the following
properties:
1. One syntax for all instructions: OPERATION.FIELD ARGS
ARGS is zero or more register names and constants separated by commas.
This syntax simplifies reading, writing, assembly, and disassembly.
2. Translations emphasize orthogonality (what little there is).
The hex translations of instructions are decomposed into tables
according to the field and register(s) to be operated on. This has
simplified the writing of a declaritive assembler/disassembler in
Prolog. You can pick up the use of these tables very quickly.
3. All instructions that do the same operation have the same name.
For example, all instructions that move data into register C
have the form:
MOVE.f x,C
4. The mnemonics are much more like those of other processors.
Sample Program
==============
Here is a sample program called SCR. It scrolls the display memory.
SCR: ; scroll the display one pixel upwards.
132 swap.a a,d0 ; save D0
103 move.w a,r3 ; in A.
D2 clr.a c ; set address field of C to 0.
3122 move.p2 #22,c ; each 1/2 of LCD is 34*2 columns (+1 on right)
27 move.1 7,p ; point to nibble 7.
307 move.p1 7,c ; nibble 7 gets 0111 bit mask.
10A move.w c,r2 ; we'll want to use these values twice.
A81 clr.p b ; B is a flag, when set it is also a bit mask.
1B048FF move.5 #FF840,d0 ; starting address of left columns of LCD.
LOOP: ; a 34 cycle loop in a 2 cycle loop: 2 * 34 * 2 = 136 columns.
1527 move.w @d0,a ; read two columns (64 bits) into A.
81C srb.w a ; shift them right (scroll up).
0E06 and.p c,a ; mask out bit shifted from first column.
1507 move.w a,@d0 ; put back the scrolled columns.
16F add.a 16,d0 ; next two columns (16 nibbles hence).
CE dec.a c ; decrement and test the lower five nibbles of
8AE9E brnz.a c,LOOP ; C that we are using as a counter.
90D31 brnz.p b,FINISH ; B==1 means we have done both sides of LCD.
1B00CFF move.5 #FFC00,d0 ; starting address of right columns of LCD.
11A move.w r2,c ; yet another set of 34 double columns to do.
A85 move.p c,b ; set the flag indicating last time through.
64DF jump LOOP
FINISH: ; do the remaining column and exit.
1561 move.wp @d0,c ; read 32 bits (reg A didn't work).
81E srb.w c ; shift column right (scroll up).
0E05 and.p b,c ; mask out bit shifted from first column.
1541 move.wp c,@d0 ; put back (or maybe reg A didn't work here).
20 move.1 0,p ; you must always restore P to 0.
113 move.w r3,a ; time to restore D0.
132 move.a a,d0 ; start dispatch.
142 move.a @d0,a ; where we go next.
164 add.a 5,d0 ; make D0 ready for the next guy to dispatch.
808C jump @a ; bye-bye...
________________________________________________________________
The information in these notes comes from my own experiments,
from public HP documents, and from some non-HP documents.
Foremost among the latter is the book, "Customize Your HP-28"
by W.A.C. Mier-Jedrzejowicz. This book contains a great deal
of valuable information about every aspect of the HP28. It is
available from:
SYNTHETIX
P.O. Box 1080
Berkeley, California
94701-1080, USA
(415)339-0601
Thanks to Dave Kaffine for explaining the new instructions.
________________________________________________________________
HP28S PROCESSOR ARCHITECTURE Version 1
Copyright (C) 1989, Alonzo Gariepy
================================================================
Overview
========
The HP28 (Saturn) CPU uses 64 bit data registers and 20 bit address
registers. The unit of addressibility is a four bit nibble, hence
the address space of the processor is 2^20 nibbles or half a megabyte.
The HP28S address space contains 128 kilobytes of ROM at addresses
#00000 to #3FFFF, and 32 kilobytes of RAM at addresses #C0000 to
#CFFFF. The RAM is aliased at addresses #D0000 to #DFFFF. Other
little chunks of the address space are used here and there for
hardware control.
Most operations on data registers can be restricted to particlar
ranges of nibbles, called fields. These fields have been chosen to
optimize the floating point arithmetic of the calculator. The format
for floating point numbers is a 1 nibble sign, followed by a 12
nibble mantissa and 3 nibble exponent, making 16 nibbles or 64 bits
in all.
The four data registers are called A, B, C, and D. The instruction
set does not allow these registers to be used interchangeably. For
example, registers A and B never interact with register D. Memory
operations are restricted to data registers A and C with the bulk of
the responsibility on register C.
There is a 4 bit pointer register, called P, that is used to specify
the position of a one nibble field (.P) or the length of a multi-nibble
field (.WP).
The two 20 bit address registers are called D0 and D1 (go figure)
and can be used interchangeably.
There are five 64 bit temporary registers called R0, R1, R2, R3, and
R4. The operations they support are restricted to moving and swapping
with registers A and C.
The HP28S system software uses some of the above registers for its
own purposes.
Register B points to the end of the object heap growing up toward the
stack. Register D1 points to the end of the stack growing down
toward the heap. Register D holds the size of the free area in
between. When it reaches zero, the stack and heap have met and its
time to garbage collect. Garbage collection creates free space by
discarding unused objects from the heap and compacting what is left.
Memory is allocated in units of 5 nibbles. The MEM function
calculates the number of free bytes by performing garbage collection
and then multiplying D by 2.5. Register P is assumed always to be
zero. D0 is the RPL instruction pointer.
If you change any of these registers (B, D1, D, P, D0) in your
machine code programs, restore their previous values before exiting.
Fields
======
Each 64 bit register comprises 16 nibbles that can be grouped into
fields for calculation and data movement. These nibbles are numbered
from right to left starting at 0; nibble 0 is the low order or least
signficant nibble and nibble 15 is the high order or most significant
nibble:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 15| 14| 13| 12| 11| 10| 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
In the following diagrams, each nibble within a field is marked with
its position, while those outside are blank. The vertical bar has
been removed from between the nibbles of a field.
Field: .P Name: Pointer Field
Start: nibble P Size: 1 nibble Example: RETZ.P B
+---+- - - -+---+---+---+- - - -+---+---+
| | | | P | | | | |
+---+- - - -+---+---+---+- - - -+---+---+
Field: .WP Name: Word to Pointer Field
Start: nibble 0 Size: P+1 nibbles Example: OR.WP C,D
+---+- - - -+---+---+---+- - - -+---+---+
| | | | P P-1 1 0 |
+---+- - - -+---+---+---+- - - -+---+---+
Field: .XS Name: Exponent Sign Field
Start: nibble 2 Size: 1 nibble Example: NOT.XS C
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | | | | | | | | | | | | | 2 | | |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .X Name: Exponent Field
Start: nibble 0 Size: 3 nibbles Example: SUB.X A,C
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | | | | | | | | | | | | | 2 1 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .S Name: Sign Field
Start: nibble 15 Size: 1 nibble Example: CLR.S B
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 15| | | | | | | | | | | | | | | |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .M Name: Mantissa Field
Start: nibble 3 Size: 12 nibbles Example: MOVE.M B,C
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | 14 13 12 11 10 9 8 7 6 5 4 3 | | | |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .B Name: Byte Field
Start: nibble 0 Size: 2 nibbles Example: INC.B C
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | | | | | | | | | | | | | | 1 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .W Name: Word Field
Start: nibble 0 Size: 16 nibbles Example: SWAP.W A,R2
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .A Name: Address Field
Start: nibble 0 Size: 5 nibbles Example: ADD.A 5,D1
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| | | | | | | | | | | | 4 3 2 1 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Field: .n Name: n Nibble Field
Start: nibble 0 Size: n nibbles Example: MOVE.8 @D0,A
+---+- - - -+---+---+---+- - - -+---+---+
| | | |n-1 n-2 1 0 |
+---+- - - -+---+---+---+- - - -+---+---+
Field. .Pn Name: n from Pointer Field
Start: nibble P Size: n nibbles Example: MOVE.P3 6,C
+---+- - - -+---+---+- - - -+---+---+---+- - - -+---+
| | | |P+n-1 P+1 P | | | |
+---+- - - -+---+---+- - - -+---+---+---+- - - -+---+
Control Registers
=================
In addition to the data and address registers (A, B, C, D, R0, R1,
R2, R3, R4, D0, D1, and P) the CPU also has some registers devoted to
control, status, and I/O.
The control registers are 20 bits long and include the program
counter (PC) and the eight level return stack (RSTK). Instructions
that directly reference the PC or the return stack use all five
nibbles (the .A field).
MOVE.A reg,PC ; reg A or C
MOVE.A PC,reg ; reg A or C
MOVE.A @reg,PC ; reg A or C
SWAP.A reg,PC ; reg A or C
PUSH.A C
POP.A C
The PC and RSTK are indirectly modified by JUMP, BRANCH, CALL, and
RETURN instructions. One level of the return stack must be available
for interrupt handling, leaving seven for program use.
Status Registers
================
The status registers include: the carry bit (C), the 16 bit status
register (ST), and the 4 bit hardware status register (HST). Each
bit of these registers can be set or cleared individually and can be
tested as part of a conditional branch or return.
The lower 12 bits (.X field) of ST can be cleared, moved, or swapped
together:
CLR.X ST
MOVE.X ST,C
MOVE.X C,ST
SWAP.X C,ST
The carry bit is set or cleared indirectly by arithmetic operations.
The RETSETC and RETCLRC instructions do this directly.
The hardware status register is made up of the XM, SB, SR, and MP
flags. These can be cleared together or in any combination. The XM
bit (eXternal Module Missing) is set when the nibbles 00 are executed
(the RETSETXM instruction) which happens when you jump to nonexistent
memory. SB (the Sticky Bit) is set whenever a non-zero bit is
shifted out the right end of a register. The SR bit (Service
Request) is set by the SREQ instruction when there is an outstanding
service requests (polling). I do not know how the MP (Module Pulled)
bit is set (perhaps when power is lost).
I/O Registers
=============
Finally, there are a 16 bit input register (IN) and a 12 bit ouput
register (OUT). The input register is used to read the keyboard, and
the output register to control the beeper.
Summary
=======
Below is a table of all the registers in the CPU. Registers that
are used by the system are marked with *. The system only uses the
low 20 bits of these registers, which must be restored after use.
Since R4 and RSTK are used by interrupts, you should never change
the lower 20 bits of R4 nor PUSH/CALL more than seven addresses
onto the return stack.
16 nibbles 5 nibbles
Data Temp Addr Ctrl Stat I/O Pntr
------ ------ ------ ------ ------ ----- ------
A R0 D0* PC C IN P*
B* R1 D1* RSTK* ST ? OUT
C R2 HST
D* R3
R4*
CPU Bugs
========
The CPU has some bugs in it, instructions that do now work correctly.
I have run into some, but they are difficult to accurately characterize.
When NOTHING else explains your problem, suspect a bug in the processor.
Two bugs that I have seen explicitly stated are:
1. The 818 opcodes (ADD.f x,reg and SUB.f x,reg) don't always work as
advertised. To be specific, when the field of such an instruction is
XS, S, P, or WP, and a carry (or borrow) is generated out of the most
significant nibble, it wraps around and affects the least significant
nibble. (Reference: Dave Kaffine).